1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming a layer of silicon on a layer of silicon/germanium.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NFET and PFET transistors) represent one important type of circuit element that substantially determines the performance capabilities of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer. A basic field effect transistor comprises a source region, a drain region and a channel region extending between the source and drain regions. Such a transistor further includes a gate insulation layer positioned above the channel region and a gate electrode positioned above the gate insulation layer. When an appropriate voltage is applied to the gate electrode, i.e., a voltage that exceeds the threshold voltage of the transistor, the channel region becomes conductive and current may flow from the source region to the drain region. The gate electrode may be made of a variety of materials, e.g., polysilicon, one or more layers of metal or combinations thereof. The gate structure of the transistor may be made using so-called “gate-first” or “replacement gate” techniques. In one embodiment, the basic structure of a field effect transistor is typically formed by forming various layers of material and thereafter patterning those layers of material using known photolithography and etching processes. Various doped regions, e.g., source regions, drain regions, halo regions, etc., are typically formed by performing one or more ion implantation processes through a patterned mask layer using an appropriate dopant material, e.g., an N-type dopant or a P-type dopant, to implant the desired dopant material into the substrate. The particular dopant selected depends on the specific implant region being formed and the type of device under construction, i.e., an NFET transistor or a PFET transistor. During the fabrication of complex integrated circuits, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate by performing a number of process operations.
In some cases, recessed source/drain regions are formed in the substrate adjacent the gate structure to improve device performance. For example, in PFET transistors, it is common practice to form recessed source/drain regions that are filled with one or more layers of silicon/germanium. Such source/drain regions are also sometimes referred to as “raised” source/drain regions because some of the semiconductor material that is used to form the source/drain regions sometimes is positioned above the upper surface of the substrate, although such a “raised” configuration is not depicted in the attached figures.
FIGS. 1A-1D depict one illustrative process flow for forming illustrative and simplistically depicted recessed source/drain regions. FIG. 1A is a simplified view of an illustrative transistor 100 at an early stage of manufacturing. The transistor 100 is formed in and above an active region 11 of a semiconducting substrate 10 that is defined by an illustrative trench isolation structure 12 formed in the substrate 10. Several process operations have been performed on the transistor 100 at the point of fabrication depicted in FIG. 1A. Initially, the illustrative isolation structures 12 were formed in the substrate 10 to thereby define the active region 11. Also depicted in FIG. 1A is a gate structure 14 (comprised of an illustrative gate insulation layer 14A and an illustrative gate electrode 14B), a gate cap layer 15 that is formed above the gate electrode 14B, and sidewall spacers 17. Although not depicted in the drawings, at the point of fabrication depicted in FIG. 1A, so-called halo implant regions (not shown) have been formed in the substrate 10, typically by performing an angled ion implant process (with a P-type dopant for an NFET transistor and with an N-type dopant for a PFET transistor) and extension implant regions (not shown) have been formed in the substrate 10 prior to forming the sidewall spacers 17.
Next, as shown in FIG. 1B, one or more etching processes are performed to define a plurality of recesses or cavities 16 in the substrate 10 proximate the gate structure 14. The depth of the recesses 16 may vary depending on the particular application, e.g., 40-55 nm. Next, as shown in FIG. 1C, one or more layers of a semiconductor material 18, typically silicon/germanium, are formed in the recesses 16 by performing one or more selective epitaxial deposition processes during which a dopant material, such as a P-type dopant material (for a PFET transistor), may be introduced in situ as the layer(s) of semiconductor material 18 is/are being formed.
The depiction of the semiconductor material 18 as a block of material in FIG. 1C is intended to be representative of any of a variety of techniques employed to fill the recesses 16 with semiconductor material. For example, in one illustrative embodiment, the semiconductor material 18 may be comprised of a single layer of silicon/germanium with a germanium concentration of about 25%. In another example, the semiconductor material 18 is comprised of two layers of silicon/germanium: a first layer of silicon/germanium having a thickness of about 20-25 nm and a germanium concentration of about 22-25% that is initially formed in the recesses 16; and a second layer of silicon/germanium having a thickness of about 400-500 nm and a germanium concentration of about 30-45% that is formed on the first layer of silicon/germanium. In yet another example, the semiconductor material 18 may be comprised of three layers of silicon/germanium: a first “seed” layer of silicon/germanium having a thickness of about 20-25 nm and a germanium concentration of about 22-25% that is initially formed in the recesses 16; a second layer of silicon/germanium having a thickness of about 40-50 nm and a germanium concentration of about 22-25% that is formed on the first layer of silicon/germanium; and a third layer of silicon/germanium having a thickness of about 5-25 nm and a germanium concentration of about 40% that is formed on the second layer of silicon/germanium. Other process schemes may also be employed to form the schematically depicted semiconductor material 18 in the recesses 16.
Next, as shown in FIG. 1D, a silicon cap layer 20 is formed above the semiconductor material 18 for a variety of purposes. One purpose of the silicon cap layer 20 is to provide material for the formation of a metal silicide region (not shown) for purposes of reducing the contact resistance between the source/drain region of the transistor and a conductive contact (not shown) that will be formed to establish electrical connection to the source/drain regions. Simply put, there must be a sufficient amount of silicon material 20, e.g., about 20 nm or more, above the source/drain regions at the time the metal silicide formation process is performed so as to enable the formation of a stable metal silicide region. If there is insufficient silicon material 20 when the metal silicide regions are formed, then there is a possibility of producing a transistor device 100 with reduced performance capabilities and/or one that is completely non-functional. Thus, in the case where about 20 nm of silicon is required for proper metal silicide formation, the silicon cap layer 20 may be manufactured “extra thick”, e.g., to a thickness of about 30-40 nm, in an attempt to avoid the problems that may occur should there not be enough silicon present during the silicide formation process. In a typical process, the silicon cap layer 20 was formed by performing a epitaxial deposition process at a temperature within the range of about 550-900° C. using, for example, silane as a precursor gas. Typical silicon deposition rates using such a prior art process were relatively low, e.g., about 4-8 Å/sec.
Another problem that device manufacturers have to account for is the fact that the silicon cap layer 20 will be exposed to several additional cleaning and/or etching processes that are performed to manufacture other aspects of the device 100. For example, the layer of silicon 20 may be exposed to cleaning/etching processes that involve use of APM or SC1 (a mixture of ammonia hydroxide, hydrogen peroxide and water). Unfortunately, these additional cleaning and/or etching processes consume portions of the layer of silicon 20. Thus, to insure that there is a sufficient amount of silicon material 20 for the metal silicide formation process, device manufacturers tend to make the layer of silicon 20 relatively thick, e.g., about 40-50 nm, to account for the unavoidable loss of the silicon material during the aforementioned cleaning and/or etching processes. This “solution” is problematic because, given the relatively low deposition rates of silicon noted above, the formation of such relatively thick layers of silicon 20 is a very time-consuming process that is not very well-suited for the high-volume, high-speed production environment that is the norm in the mass production of integrated circuit products.
The present disclosure is directed to various methods that may reduce or eliminate one or more of the problems identified above.